package uart
 
import chisel3._
import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
import firrtl.options.TargetDirAnnotation

import uart._

object verilog_Uart_top extends App {
    (new chisel3.stage.ChiselStage).execute(
        Array("-X", "verilog", "--full-stacktrace"),
        Seq(ChiselGeneratorAnnotation(() => new UART_top()),
        // TargetDirAnnotation("/home/zhangshen/workspace/PUF/projects/puf/vsrc"))
        TargetDirAnnotation("generated/uart/"))
    )
}